Output characteristics of a circuit for high-speed communication such as the one through USB (Universal Serial Bus) 2.0 are defined by extremely strict specifications. The USB 2.0 is present is a personal computer interface specification for connecting a peripheral device. A result of an individual design product is evaluated by conducting a certification test and judging whether its characteristics conform to a specification by a specific organization. Characteristics of semiconductor integrated circuits vary according to process variations, a temperature variation, or a supply voltage variation. Thus, it is not so easy to satisfy the specifications under all requirements. In recent years, semiconductors of higher-speed, larger-size, and higher power consumption have become popular, and a junction temperature of the semiconductors greatly changes according to an operation state of the semiconductors. Accordingly, the driver circuit is particularly desired which sufficiently satisfies the specifications even if a large temperature variation would occur.
FIG. 5 is a circuit diagram of a driver circuit of a conventional art. Referring to FIG. 5, the driver circuit includes a differential pre-buffer circuit 101, a differential output circuit 102, and a constant current circuit 103. Reference numeral 1 denotes a power supply terminal. Reference numeral 2 denotes a non-inverted input terminal (+), reference numeral 3 denotes an inverted input terminal (−), reference numeral 4 denotes a GND terminal, reference numerals 5 to 12 denote P-ch MOS transistors, reference numerals 13 to 15 denote N-ch MOS transistors, reference numerals 16 and 17 denote diodes, reference numerals 18 and 19 denote terminating resistances for outputs, reference numeral 20 denotes a non-inverted output terminal (+), and reference numeral 21 denotes an inverted output terminal (−).
The constant current circuit 103 has a configuration as shown in FIG. 6. Referring to FIG. 6, a reference voltage circuit 61 is a stable reference voltage source such as a band gap regulator, and supplies a stable voltage to a non-inverted input terminal of an operational amplifier 62. An output terminal of the operational amplifier 62 is connected to a gate of an N-ch MOS transistor 63 in an output stage. A source of the N-ch MOS transistor 63 is connected to a voltage output terminal 64 and an inverted input terminal of the operational amplifier 62. Between the voltage output terminal 64 and a GND (for grounding), an external resistance 65 for an LSI is connected. A drain of the N-ch MOS transistor 63 in the output stage is connected to an input side of a current mirror circuit constituted from P-ch MOS transistors 66 and 67. An output of the current mirror is input to a current mirror constituted from N-ch MOs transistors 68 and 69. From a current output terminal 25 connected to a drain of an N-ch MOs transistor 69, an output current Iref is output.
When an output voltage of the reference voltage circuit 61 is represented by Vref and a value of the external resistance 65 is represented by Rref, an output current Iref from the current output terminal 25 for the current mirror is expressed by Equation (1).Iref=Vref/Rref  Equation (1)When the voltage Vref is set to have small variations and a small temperature variation and when the resistance Rref is set to have neither variations nor temperature variation, both the variations of the current Iref and the temperature variation of the current Iref become extremely small. An output current I0 (Iref) of the constant current circuit 103 is a current of which the variations and the temperature variation are both small. The output current I0 is input to a current mirror circuit constituted from P-ch MOS transistors 5 to 8.
A drain current I1 of the P-ch MOS transistor 7 is the current from a constant current source for P-ch MOS transistors 9 and 10 in the differential stage of a differential pre-buffer circuit 101. A drain of the P-ch MOS transistor 6 is connected to an input side of a current mirror constituted from the N-ch MOS transistors 13 to 15. Drains of the N-ch MOS transistors 14 and 15 are connected to drains of the P-ch MOS transistors 9 and 10, respectively. Further, the drains of the N-ch MOS transistors 14 and 15 are connected to anodes of diodes 16 and 17, respectively, and are also connected to points A and B, respectively, which become output terminals of the differential pre-buffer circuit 101. When drain currents of the N-ch CMOS transistors 14 and 15 are set to be equal and the value of the currents is represented by I2, the currents I1 and I2 both become constant currents of which both of the variations and the temperature variation are small.
The P-ch MOS transistors 11 and 12 in the differential stage of the differential output circuit 102 receives an output current I3 of the P-ch MOS transistor 8, which is an output of the current mirror circuit, as a constant current. The terminating resistance 18 is connected between the output terminal 20 and a GND, and the terminating resistance 19 is connected between the output terminal 21 and the GND. The current I3 is likewise the constant current of which both the variations and the temperature variation are small. Accordingly, when a resistance of which both the variations and the temperature variation are small (such as an external resistance) is employed for the terminating resistances 18 and 19, the variations and temperature variation of amplitudes of outputs of the output terminals 20 and 21 will also become small.
FIG. 7 shows operating waveforms of respective points. When input signals that are inverted to each other are supplied to the non-inverted input terminal (+) 2 and the inverted input terminal (−) 3, signals with the waveforms thereof as shown in FIG. 7 are output from the points A and B, at which outputs of the differential pre-buffer circuit 101 appear, and the non-inverted output terminal (+) 20 and the inverted output terminal (−) 21 of the differential output circuit 102.
When an input capacitance of each of the P-ch MOS transistors 11 and 12 in the differential stage of the differential output circuit is represented by Cin and when this is set to be sufficiently larger than other parasitic capacitance, a rise time and a fall time at the points (nodes) B and A are expressed by Equations (2) and (3), respectively, as shown in FIG. 8:Rise Time=(I1−I2)/Cin  Equation (2)Fall Time=I2/Cin  Equation (3)Since the capacitance Cin is the input capacitance of a CMOS transistor, the temperature variation of the capacitance Cin is small. Accordingly, the rise and fall times of the output waveforms at the output terminals 20 and 21 depend on the rise and fall times of outputs A and B of the pre-buffer circuit 101. Thus, the output waveforms of which the variations and the temperature variation are small can be obtained.